clockgen Project Status (12/07/2010 - 12:31:28)
Project File:	clockgen.xise	Parser Errors:	No Errors
Module Name:	clockgen	Implementation State:	Fitted
Target Device:	xc9536xl-5VQ44	Errors:	No Errors
Product Version:	ISE 12.3	Warnings:	4 Warnings (4 new)
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue 7. Dec 12:31:15 2010	0	4 Warnings (4 new)	0
Translation Report	Current	Tue 7. Dec 12:31:18 2010	0	0	0
CPLD Fitter Report (Text)	Current	Tue 7. Dec 12:31:21 2010	0	1 Warning (1 new)	1 Info (1 new)
Power Report

 

Secondary Reports			[-]
Report Name	Status	Generated
Post-Fit Simulation Model Report

Date Generated: 12/07/2010 - 12:31:29